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Clock gating support? #50
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Original Redmine Comment After looking at the _eval event loop generated by verilator , I don't see how generated clocks could work consistently when there is feedback in the design. There seems to be a definite ordering of the events inside eval loop and I see my different generated clocks in there. I apologize if I misunderstood the internal workings of the verilator in some way. To support latches and gated clocks I think verilator needs support for an expanded event queue. Maybe not as elaborate as the Verilog standard, but at least support for "non-blocking" events. Let me know if I can help out in any way. You don't want me touching the code:-) but I can definitely help in testing and brain storming. The verilog standard event queue. 1.) Events that occur at the current simulation time and can be processed in any order. These are the |
Original Redmine Comment First, using the clock_enable pragma is fine. I updated the docs You're right how the event queue works for an event simulator. However Verilator instead computes the event ordering internally then optimizes; this is a lot more complicated (and bug prone) but more than 2x faster. As for your problem, can you reduce it to a little testcase as |
Original Redmine Comment Hi Wilson, Thanks for the quick reply. I find it ironic (and quite funny) that your open source support is faster than most commercial EDA support:-) I will work on a test case packaged up the right way. Here is the code of the test case. (I verified it with Icarus). There is a race at flop3 when handing off data from flop2. Is there a better way of dealing with generated clocks? In this case, driving all clocks at the interface is not an option. TESTCASE:
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Believed fixed in develop-v5 with #3278. |
Author Name: Andreas Olofsson
Original Redmine Issue: 50 from https://www.veripool.org
Original Date: 2009-01-20
What is the status of clock gating support? The documentation mentions putting clock_enable on clock enable signals, but it says the feature is experimental.I am getting failures with clock gating and I am pretty sure it's glitch related.
Here is my clock gating construct.
always @ (/AS/clk or en)
if(~clk)
en_sh <=en;
assign qclk = clk & en_sh
In some simulators there would usually be a way to debug these phantom glitches by "expanding an event". What would be the best way to debug this problem in verilator generated code. It might be a good thing to add to the FAQ.
Andreas
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