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assign with value containing newline fails #507

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veripoolbot opened this issue May 7, 2012 · 2 comments
Closed

assign with value containing newline fails #507

veripoolbot opened this issue May 7, 2012 · 2 comments
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Author Name: Walter Lavino
Original Redmine Issue: 507 from https://www.veripool.org
Original Date: 2012-05-07
Original Assignee: Wilson Snyder (@wsnyder)

Wilson,

The verilog parser would fail in case a white space is found after the 'h'

module any_logic ();

 assign AA_DATA = {8'h00};  // OK

 assign BB_DATA = {8'h

00}; // FAILS

endmodule; // any_logic

Error Message:
%Error: filename.v:6: syntax error, unexpected INTEGER NUMBER, expecting ',' or '}'

regards,
Walter
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-07T12:35:36Z

It's the newline, not the spaces.

The parser originally predated Verilog 1995 standard and so needs to see a complete verilog number with optional spaces. For now I fixed newlines, but this ideally requires rework to allow comments and such between the parts, and is related to fixing #�.

Newline part of fix in git towards 3.316.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-27T22:51:17Z

In 3.316.

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