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signed/unsigned mixed calculation with WIDTH warning off #511

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veripoolbot opened this issue May 9, 2012 · 3 comments
Closed

signed/unsigned mixed calculation with WIDTH warning off #511

veripoolbot opened this issue May 9, 2012 · 3 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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Author Name: junji hashimoto
Original Redmine Issue: 511 from https://www.veripool.org
Original Date: 2012-05-09
Original Assignee: Wilson Snyder (@wsnyder)

I think signed/unsigned mixed calculation is wrong.

Sample code is below.

module mod(A);
output [7:0] A;
wire [7:0] B;
wire signed [3:0] C;
assign C=-1;
assign B=3;
assign A=B+C;
endmodule

Verilator outputs A=-2(Wrong)
But
NC-Verilog outputs A=18(Correct)

In this case,
all number have to use unsigned.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-09T02:48:51Z

You'll note Verilator gave a WIDTH warning about this; you must have turned that warning off. When it has to width extend a signed number it lost the expansion was being done in an unsigned context. Need a big edit to fix this, so patch in a day or so.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-17T02:19:13Z

Fixed in git towards 3.840++.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-31T22:55:06Z

In 3.840.

@veripoolbot veripoolbot added area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed labels Dec 22, 2019
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed
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