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Loop causes internal error #513

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veripoolbot opened this issue May 10, 2012 · 4 comments
Closed

Loop causes internal error #513

veripoolbot opened this issue May 10, 2012 · 4 comments
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@wsnyder
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resolution: fixed Closed; fixed

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 513 from https://www.veripool.org
Original Date: 2012-05-10
Original Assignee: Wilson Snyder (@wsnyder)

The following code has a loop dependency between the first two always blocks. It should execute to completion on the first positive clock edge.

module t (clk);
    input clk;
    reg 	 ready;

    initial begin
       ready = 1'b0;
    end
    
    always @(posedge ready) begin
       if ((ready === 1'b1)) begin
	 $write("*-* All Finished *-*\n");
	 $finish;
       end
    end

    always @(posedge ready) begin
       if ((ready === 1'b0)) begin
          ready = 1'b1 ;
       end
    end

    always @(posedge clk) begin
       ready = 1'b1;
    end
endmodule

This works fine on Icarus Verilog, but on Verilator fails to compile, with the error:

%Error: Internal Error: ../V3GraphAcyc.cpp:343: Non-cutable edge forms a loop   VERTEX=0x8bd71c0\n ALWAYS

(The example is meaningless, but was obtained by cutting down a 1100 line proprietary code where the error occurred).

Please pull the testcase from https://github.com/jeremybennett/verilator/tree/loop-crash.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-10T22:33:44Z

I'm not sure how to best report this error, as the code requires an event driven simulator. Perhaps as a multidriven non-blocking error. Or just change the uncuttable to a more obvious filename/line number pointer.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-11T00:41:33Z

These would have gotten a BLKSEQ warning, but BLKSEQ is a lint-style-only warning.

Looks like the loop detection logic is the only place that sees the complicated picture, so it will need to print an example path out by calling loopsVertexCb.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-16T23:31:49Z

Better error message, fixed in git towards 3.900+.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-31T22:56:00Z

In 3.840.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
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