Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 514 from https://www.veripool.org
Original Date: 2012-05-15
Original Assignee: Wilson Snyder (@wsnyder)

Probably a result of recent upgrades to tristate handling, this reportedly worked in the past.

module t (clk);
    input clk;

    wire [11:0] ck;

    assign ck[1:0] = {1'bz,{1{1'b0}}};

    test i_test (.clk (ck[1:0]));

endmodule
 
module test (clk);

    output wire [1:0] clk;

endmodule // test

Gives the error:

%Error: t/t_tri_graph.v:21: Unsupported tristate construct (in graph; not converted): SEL

where line 21, is the line instantiating the sub-module.

Please pull a testcase from https://github.com/jeremybennett/verilator/tree/tristate-graph