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Author Name: Alex Solomatnikov
Original Redmine Issue: 516 from https://www.veripool.org
Original Date: 2012-05-17
Original Assignee: Wilson Snyder (@wsnyder)
In complex designs with multiple instances of the same module, verilator generates multiple warnings for the same issue, e.g.:
%Warning-WIDTH: ...mc_channel.v:575: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'atc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:582: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'dlc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:575: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'atc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:582: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'dlc_req_uop_in' generates 4 bits.
Of course, this is not critical issue.
The text was updated successfully, but these errors were encountered:
Author Name: Alex Solomatnikov
Original Redmine Issue: 516 from https://www.veripool.org
Original Date: 2012-05-17
Original Assignee: Wilson Snyder (@wsnyder)
In complex designs with multiple instances of the same module, verilator generates multiple warnings for the same issue, e.g.:
Of course, this is not critical issue.
The text was updated successfully, but these errors were encountered: