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Issue #526

Support UVM

Added by Jan Seyler over 7 years ago. Updated about 1 month ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
% Done:

0%


Description

It would be great for the parser to support UVM!

History

#1 Updated by Wilson Snyder over 7 years ago

  • Status changed from New to Feature

The parser at present needs to know what is a class etc when tokens are recognized. However it's easily confused when a new symbol is declared that overrides an old symbol. For example, making a variable/function of the same name of what was a class, or vice-versa. UVM confusingly (for the users) does this all over the place. For example below foo is a class, then becomes a function.

typedef class uvm_component;
class foo extends uvm_component;
  function foo();
  endfunction
endclass

While it might be possible to further extend the lexing, this seems a bad idea. Instead the parser needs to handle the grammar ambiguities that arise from not knowing if something is a class or not until later in the parse. This means the grammar is no longer LAR but GLR. Thus the parser needs to switch to use either bison in GLR mode, or perhaps give up and go to ANTLR. ANTLR is probably better as it's a route known to work in SystemVerilog since some commercial products use it (or at least mention the ANTLR copyright, so one presumes....)

Obviously this is a great deal of work.

#2 Updated by Wilson Snyder over 7 years ago

  • Tracker changed from 2 to Issue

#3 Updated by Wilson Snyder about 1 month ago

  • Status changed from Feature to WillNotFix

The verilog-perl parser is unlikely to be improved beyond current support. Attention is instead being given to the Verilator parser which is marching towards UVM. Or use one of the other open source parsers.

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