module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;

    integer   cnt = 0;

    reg [1:0] y1;

`ifndef VERILATOR
    initial begin
       $dumpfile("obj_dir/iv_t_eval_problem6/iv_t_eval_problem6.vcd");
       $dumpvars;
    end
`endif

    initial begin
       y1 = 0;
    end

    always @(clk) begin
       y1 = y1 + 1;
    end

    always @(posedge clk) begin
       cnt = cnt + 1;
    end

    always @(clk) begin
`ifdef TEST_VERBOSE
       $display("clk = %x, y1 = %x", clk, y1);
`endif
       if (cnt > 4) begin
          $write("*-* All Finished *-*\n");
          $finish;
       end
    end

endmodule

%Warning-UNOPTFLAT: t/t_eval_problem6.v:17: Signal unoptimizable: Feedback to clock or circular logic: v.y1
%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
%Warning-UNOPTFLAT:      Example path: t/t_eval_problem6.v:17:  v.y1
%Warning-UNOPTFLAT:      Example path: t/t_eval_problem6.v:30:  ALWAYS
%Warning-UNOPTFLAT:      Example path: t/t_eval_problem6.v:17:  v.y1