Missing width warning when part of a bus is compared #533
Labels
area: data-types
Issue involves data-types
area: lint
Issue involves SystemVerilog lint checking
effort: days
Expect this issue to require roughly days of invested effort to resolve
resolution: wontfix
Closed; work won't continue on an issue or pull request
Author Name: Chandan Egbert
Original Redmine Issue: 533 from https://www.veripool.org
Original Date: 2012-07-20
Verilator generates incorrect code for the comparison
where the total width of "a" is larger than m. The comparison in the following example
should produce the value 1 when a is 0xffff. However, it produces the value 0.
An example in the verilator test_regress style is attached.
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