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Author Name: Brad Dobbie
Original Redmine Issue: 540 from https://www.veripool.org
Original Date: 2012-07-31
Original Assignee: Wilson Snyder (@wsnyder)
I'm not sure if this was intended behavior, but when AUTOINSTing an interface illegal code is generated.
The signals marked as "Interfaced" are not declared as ports and cannot be connected via instantiation.
Error-[UPIMI-E] Undefined port in module instantiation
project/verif/vkits/iox/auto_module.v, 21
Port "req_val" is not defined in interface 'auto_intf' defined in
"project/verif/vkits/iox/auto_intf.sv", 4
Interface instance: auto_intf auto_i( .req_val (req_val), .req_data
(req_data[63:0]), .req_credit (req_credit), .rsp_cmd (rsp_cmd[1:0]),
.rsp_data (rsp_data[63:0]), .rsp_cre ...
The text was updated successfully, but these errors were encountered:
Author Name: Brad Dobbie
Original Redmine Issue: 540 from https://www.veripool.org
Original Date: 2012-07-31
Original Assignee: Wilson Snyder (@wsnyder)
I'm not sure if this was intended behavior, but when AUTOINSTing an interface illegal code is generated.
Given an interface:
AUTOINST generates the following:
The signals marked as "Interfaced" are not declared as ports and cannot be connected via instantiation.
The text was updated successfully, but these errors were encountered: