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Question: Issue with hooking up ports using conditional operators #564

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veripoolbot opened this issue Sep 24, 2012 · 3 comments
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Author Name: Gauravg Gupte
Original Redmine Message: 915 from https://www.veripool.org


I’m using AUTO_TEMPLATE to conditionally connect outputs to different names depending on the instance number using the following syntax for a "if" statement.
.GcuSSArb(.*)VecNnnW (@"(if (= (% @ 2) 0) \"GcuReqArbGntVec0NnnW[@"(/ @ 2)"]\" \"GcuReqArbGntVec1NnnW[@"(/ @ 2)"]\")"),

All I want to do is hook up GcuReqArbGntVec0NnnW to even instances and GcuReqArbGntVec1NnnW to odd instances.(and use the expressions above to connect correct bits of the vector). However I get and end of file parsing error when I run AUTOS. However; if I try and do these expressions individually both of them work:

For instance:
.GcuSSArb(.*)VecNnnW (@"(if (= (% @ 2) 0) \"GcuReqArbGntVec0NnnW[]\" \"GcuReqArbGntVec1NnnW[]\")"), // THIS WORKS WITH AUTOS

OR

.GcuSSArb(.*)VecNnnW (GcuReqArbGntVec0NnnW[@"(/ @ 2)"]), // THIS WORKS WITH AUTOS

But when I try to put these 2 together it doesnt go through. Anything I am doing wrong? Is there any workaround to this?

Gaurav

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-09-24T18:55:16Z


Looks reasonable to me. Check you are using the most recent verilog-mode version, and if so paste a complete small example showing the problem and I'll take a look.

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Original Redmine Comment
Author Name: Sathappan Palaniappan
Original Date: 2014-06-06T23:54:44Z


Is there a way to check more than one conditions?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-07T13:43:50Z


It's lisp. For example "(cond" or use some nested "(if".

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