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Author Name: Chandan Egbert
Original Redmine Issue: 567 from https://www.veripool.org
Original Date: 2012-10-13
Original Assignee: Chandan Egbert
This code
module sub();
endmodule
module un(input logic a, input logic b,
output logic x, output logic y);
always_comb begin
integer i;
x = a;
end
sub u0();
always_comb begin
integer j;
y = b;
end
endmodule
causes Verilator 3.841 to bail out with the following error:
%Error: unnamedblk.v:16: Duplicate declaration of block: unnamedblk1
%Error: unnamedblk.v:8: ... Location of original declaration
removing the instantiation of the sub module "sub" or removing the declaration of one of the variables i or j makes the error message go away.
The text was updated successfully, but these errors were encountered:
Author Name: Chandan Egbert
Original Redmine Issue: 567 from https://www.veripool.org
Original Date: 2012-10-13
Original Assignee: Chandan Egbert
This code
causes Verilator 3.841 to bail out with the following error:
removing the instantiation of the sub module "sub" or removing the declaration of one of the variables i or j makes the error message go away.
The text was updated successfully, but these errors were encountered: