Author Name: Tom Smith
Original Redmine Message: 944 from https://www.veripool.org

Hi All,
Just started using verilog-mode and had a few questions to setup my indents.

Currently I get the following with the default settings:

typedef enum logic {
                     APPLE = 1'b0,
                     ORANGE = 1'b1
                     } FRUIT_t;

What settings do I need to change to get the following. Have played around with multiple settings but can't get it right:

typedef enum logic {
    APPLE = 1'b0,
    ORANGE = 1'b1
} FRUIT_t;