Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 576 from https://www.veripool.org
Original Date: 2012-11-07

@generate@/@endgenerate@ are required in Verilog 2001, but not in 2005. So the following code should generate an error with Verilog 2001.

// This is a Verilog 2005 test (generate/endgenerate omitted).
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
end

However this code compiles with Verilog 2001 set as the language (@--language 1364-2001@).

It's not terribly important. I found it trying to construct a test of new language extension options. Added here for the record.