module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;
    wire [71:0] ctrl;

    memory #(.words(72)) i_memory (.clk (clk));

    assign ctrl = i_memory.mem[0];
endmodule

// memory module, which is used with parameter
module memory (clk);
    input clk;

    parameter words = 16384, bits = 72;

    reg [bits-1 :0] mem[words-1 : 0];

endmodule

pure virtual method called
terminate called without an active exception
%Error: Verilator aborted.  Consider trying --debug --gdbbt