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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-12-03T03:08:31Z
This parses in Verilog-Perl. I looked at the parser differences and package scope isn't properly supported in expressions, it will be easier if I reconcile it.
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-12-31T22:07:31Z
Fixed in git towards 3.844. This required a fairly large parser change, so it might make some dotted reference (a.b.c) handling unstable, though everything I have passes.
Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 586 from https://www.veripool.org
Original Date: 2012-11-29
Original Assignee: Wilson Snyder (@wsnyder)
The following is accepted by VCS, and I believe it to be valid System Verilog:
With Verilator, this fails with:
(where line 37 is the line declaring @input logic ...@ )
I'll start investigating what is needed to extend Verilator to support this SystemVerilog syntax. I'd welcome any hints on this.
A test case for this can be pulled from branch sv-package-param at git@github.com:jeremybennett/verilator.git
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