Author Name: Leith Johnson
Original Redmine Message: 973 from https://www.veripool.org

I have a need to build some algorithmically complex state machines. This is certainly doable with Verilog and a text editor, but it can be tedious (veritedium??) to manage and maintain the state assignments.

Within the structure of the Verilog language I would like to create the notion of a program counter and symbolic branching. The basic structure is a case statement. A case label represents a line in the program.

Minimum clock cycle is not a strong requirement. Manipulating state assignments to improve performance shouldn't be required.

Accomplishling what I need is basically a two step process. First step is to scan the code, assigning values to the case labels and building a symbol table. Step 2 is scan the code again, replacing the symbols with values from the symbol table.

I'm already using AUTOs. Perhaps some enhancement so AUTOs can do what I need.

Create two new AUTOs:

/AUTO_PC(optional_symbol)/ : begin
end

pc_next_state = /AUTO_SYM(symbol)/;

Upon AUTOs evaluation, these turn in to something like:

/AUTO_PC(optional_symbol)/ 12'h001 : begin
end

pc_next_state = /AUTO_SYM(symbol)/ 12'h030;

One issue is the width/format of the state assignments. One solution might be to have AUTOs count the AUTO_PCs it encounters and do a clogb2 to come up with the pc width. This would require another pass. Another solution is to default pc width to 32 bits. A small amount of manipulation of the register assignment should provide synthesis with enough clues to eliminate the unnecessary bits, while keeping lint at bay.

I'm not attached to the idea of using AUTOs to solve this problem. In fact the best answer might be if somebody knows of a general purpose microcode assembler?? Or maybe some combination of preprocessing and AUTOs?? I'm open to any suggestion.

I've looked a bit at verilog-mode.el. My last lisp experience was in college many years ago... and there's a lot more there than I expected.

BTW, one of the really cool aspects of this is the micromachine "instructions" are limited only by what can be written in synthesizable Verilog. In my case an alternative is synthesizing a small general purpose processor. But then I'll have to create some interface layer to talk to what I'm controlling. Furthermore, talking to what I'm controlling will be through some indirect register interface. If I can get this to work out, I'll talk directly to what I'm controlling in a manner consistent with the functionality. And if I need some new instruction down the road, I'll just make it up on the fly.

Below is what it might look like without any automated symbol assignment. This little micromachine resets, waits for while after reset, then sets the output pulse_something high for 1 state out of three forever. With the way I did it, I'm trying to illustrate how maintenance can be difficult. As shown, inserting a new state between PC_Q and PC_B would require reworking all the state assignment following PC_Q.

  localparam PC_WIDTH = 8;
  localparam ONE = 1;
  localparam TWO = 2;
  localparam THREE = 3;
  localparam FOUR = 4;

  localparam [PC_WIDTH-1:0] PC_RESET = ONE[PC_WIDTH-1:0];
  localparam [PC_WIDTH-1:0] PC_A = TWO[PC_WIDTH-1:0];
  localparam [PC_WIDTH-1:0] PC_Q = THREE[PC_WIDTH-1:0];
  localparam [PC_WIDTH-1:0] PC_B = FOUR[PC_WIDTH-1:0];  

  input clk;
  input reset;

  output pulse_something;

  reg [PC_WIDTH-1:0] pc, pc_next_state;
  reg [7:0] rst_wait, rst_wait_next_state;

  always @(*) begin
     
 // RESET next states    
     if (reset == 1'b1) begin    
       pc_next_state = PC_RESET;
       rst_wait_next_state = 8'hff;
       pulse_something = 1'b0;
     end else begin

// Default next states.
       pc_next_state = pc + ONE[PC_WIDTH-1:0];
       rst_wait_next_state = rst_wait - 8'h01;
       pulse_something = 1'b0;

// PC based actions and next states. 
       case (pc)
         PC_RESET: begin
           if (rst_wait != 8'h00) pc_next_state = PC_RESET;
         end
         
         PC_A: begin
         end
         
         PC_Q: begin
           pulse_something = 1'b1;
         end
         
         PC_B: begin
           pc_next_state = PC_A;
         end
         
       end // else: !if(reset == 1'b1)
     endcase // case (pc)
  end // always @ (*)

  always @(posedge clk) pc <= pc_next_state;
  always @(posedge clk) rst_wait <= rst_wait_next_state;

Thanks in advance for any suggestions.

Leith Johnson