Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 599 from https://www.veripool.org
Original Date: 2013-01-08
Original Assignee: Wilson Snyder (@wsnyder)

SystemVerilog requires that local declarations override package declarations, where wildcard import is used with the package (IEEE 1800-2009, section 26.3). Thus the following is valid System Verilog:

package defs;
    parameter NUMBER = 8;
    localparam NUM = NUMBER;
endpackage

module t(/*AUTOARG*/
    // Inputs
    clk
    );

    input clk;
    import defs::*;

    parameter NUM = 32;
endmodule

However, although this passes with VCS, it fails with Verilator, giving a duplicate declaration warning.

Please pull a patch with the testcase from branch package-param at git@github.com:jeremybennett/verilator.git.