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Bit selection from struct causes internal error #600

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veripoolbot opened this issue Jan 9, 2013 · 2 comments
Closed

Bit selection from struct causes internal error #600

veripoolbot opened this issue Jan 9, 2013 · 2 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 600 from https://www.veripool.org
Original Date: 2013-01-09
Original Assignee: Wilson Snyder (@wsnyder)

The following code causes an internal error:

module t(/*AUTOARG*/
    // Inputs
    clk
    );

    input clk;
    typedef struct packed {
        logic [1:0][15:0] channel;
        logic others;
    } buss;

    buss b;
    wire [7:0] a;

    assign a = b.channel[0][8+:8];
endmodule

The error is:

%Error: Internal Error: t/t_bitsel_struct.v:25: ../V3LinkResolve.cpp:210: Illegal bit select; no signal/member being extracted from

The code works with VCS. Please pull the test case from branch struct-bit-sel at git@github.com:jeremybennett/verilator.git.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-15T02:53:05Z

This is fixed in git towards 3.845. This uncovered handing of packed arrays-of-structs-of-arrays was also even more broken.

To fix this packed arrays are now represented as a single linear vector in Verilated models this may affect packed arrays that are public or accessed via the VPI. This is a relatively large change that may introduce fallout, as always let me know any issues.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:21:26Z

In 3.845.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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