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bit-select with :+ and :- fails with packed structures #605

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veripoolbot opened this issue Jan 17, 2013 · 2 comments
Closed

bit-select with :+ and :- fails with packed structures #605

veripoolbot opened this issue Jan 17, 2013 · 2 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 605 from https://www.veripool.org
Original Date: 2013-01-17
Original Assignee: Jeremy Bennett (@jeremybennett)

The following code fails to compile:

    typedef struct packed {
        logic [15:0] channel;
        logic [15:0] others;
    } buss_t;

    buss_t     b;

    reg [7:0]  a;
    reg [7:0]  c;
    reg [7:0]  d;

    initial begin
       b = {16'h8765,16'h4321};
       a = b[19:12];			// This works
       c = b[8+:8];			// This fails
       d = b[11-:8];			// This fails

The problem is that @replaceSelPlusMinus()@ in @V3WidthSel.cpp@ only works for basic data types. The solution is to also allow packed struct and array datatypes.

For now, please pull a patch with the test case from branch packed-access at git@github.com:jeremybennett/verilator.git. I'm working on a fix, which I hope to post shortly.
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Original Redmine Comment
Author Name: Jeremy Bennett (@jeremybennett)
Original Date: 2013-01-17T14:29:21Z

Simple patch to also allow packed structs and arrays:

index d323be5..8f6c562 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -358,7 +358,10 @@ private:
         FromData fromdata = fromDataForArray(nodep, fromp, width!=1);
         AstNodeDType* ddtypep = fromdata.m_dtypep;
         VNumRange fromRange = fromdata.m_fromRange;
-       if (ddtypep->castBasicDType()) {
+       // Issue 605: Also allow packed structs and arrays.
+       if (ddtypep->castBasicDType()
+           || (ddtypep->castNodeClassDType()
+               && ddtypep->castNodeClassDType()->packed())) {
             AstSel* newp = NULL;
             if (nodep->castSelPlus()) {
                 if (fromRange.littleEndian()) {

Please pull the patch and testcase from branch packed-access at git@github.com:jeremybennett/verilator.git.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-18T02:49:29Z

Gotta love good tests with the fixes!

Pushed to git towards 3.845.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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