Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #609

error on array port connection

Added by Alex Solomatnikov over 6 years ago. Updated over 6 years ago.

Status:
Closed
Priority:
High
Assignee:
Category:
TranslationError
% Done:

0%


Description

RTL:

module cache
  (
   output cache_tag_t        tag_out  [`CACHE_WAYS-1:0], // Tags from all ways
...
endmodule

   cache  cache(
                         .tag_out             (tag_cache_pipe  [`CACHE_WAYS-1:0]),         

Error:

%Error: ...: Illegal port connection tag_out, port is not an array expression is an array

Not clear what the message is supposed to mean.

Used to compile in 3.842.

History

#1 Updated by Wilson Snyder over 6 years ago

  • Status changed from New to AskedReporter

Sorry, but I really need to get complete examples in the format like test_regress/t/t_EXAMPLE.v as described in the manual.

#2 Updated by Alex Solomatnikov over 6 years ago

Here is modified test from regress:

module t (/*AUTOARG*/
   // Inputs
   clk
   );
   input clk;

   logic [6-1:0] foo[4-1:0];

   dut #(.W(6),
         .D(4)) udut(.clk(clk),
                     .foo(foo[4-1:0]));
endmodule

module dut
    #(parameter W = 1,
      parameter D = 1)
    (input logic clk,
     input logic [W-1:0] foo[D-1:0]);

    genvar i, j;
    generate
       for (j = 0; j < D; j++) begin
          for (i = 0; i < W; i++) begin
             suba ua(.clk(clk), .foo(foo[j][i]));
          end
       end
    endgenerate
endmodule

module suba
  (input logic clk,
   input logic foo);

   always @(posedge clk) begin
      $write("*-* All Finished *-*\n");
      $finish;
   end
endmodule

The error:

./verilator --cc --top-module t t_bug609.v
%Error: t_bug609.v:18: Illegal port connection foo, port is not an array expression is an array.
%Error: Exiting due to 1 error(s)

Earlier version:

/tools/verilator/verilator-3.842/bin/verilator --cc --top-module t t_bug609.v

#3 Updated by Wilson Snyder over 6 years ago

The obvious fix for this breaks several tests so will take a bit longer; current support for slices which this is isn't very good, it's only that this was a complete slice that it happened to work with the old version. For now just remove the [4-1:0] from the port declaration.

#4 Updated by Wilson Snyder over 6 years ago

  • Category set to TranslationError
  • Status changed from AskedReporter to Closed
  • Assignee set to Wilson Snyder

Fixed in 3.845.

Also available in: Atom