module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;

    logic [6-1:0] foo[4-1:0];

    dut #(.W(6),
          .D(4)) udut(.clk(clk),
                      .foo(foo[4-1:0]));
endmodule

module dut
     #(parameter W = 1,
       parameter D = 1)
     (input logic clk,
      input logic [W-1:0] foo[D-1:0]);

     genvar i, j;
     generate
        for (j = 0; j < D; j++) begin
           for (i = 0; i < W; i++) begin
              suba ua(.clk(clk), .foo(foo[j][i]));
           end
        end
     endgenerate
endmodule

module suba
  (input logic clk,
    input logic foo);

    always @(posedge clk) begin
       $write("*-* All Finished *-*\n");
       $finish;
    end
endmodule

./verilator --cc --top-module t t_bug609.v
%Error: t_bug609.v:18: Illegal port connection foo, port is not an array expression is an array.
%Error: Exiting due to 1 error(s)

/tools/verilator/verilator-3.842/bin/verilator --cc --top-module t t_bug609.v