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Issue #619

Hierarchical parameter binding

Added by Ed Lander over 6 years ago. Updated over 6 years ago.

Status:
WillNotFix
Priority:
High
Assignee:
-
Category:
-
% Done:

0%


Description

Hi Wilson,

Following on from ticket #602, here is our request for an enhancement to the recently implemented bind feature.

We've been seeing the following types of messages when trying to build our full design (inc. binds):

%Error: <file>:<line>: Expecting expression to be constant, but can't convert a VARXREF '<parameter>' to constant.

%Error: <file>:<line>: Can't convert defparam value to constant: Param <parameter> of <bound_instance>

We've driven your t_bind2.v test-case through the flow, and noticed that the parameters don't include hierarchical references:

bind targetmod mycheck
  #(
    .param2(param2),
    .param3(param3)
    )
i_mycheck (.p2(p2), .p3(p3), .*);

Our original example was like this, eg:

bind i_targetmod mycheck #(
  .param2(param2),
  .param3(top.param3)
) i_mycheck(.p2(p2), .p3(top.p3), .*);

Once correcting the bind to module (not instance), we see the same Errors:

%Error: bind_example.sv:32: Expecting expression to be constant, but can't convert a VARXREF 'param3' to constant.

%Error: bind_example.sv:32: Can't convert defparam value to constant: Param param3 of i_mycheck

Simplifying the bind to this is OK:

bind targetmod mycheck #(
  .param2(param2)
) i_mycheck(.p2(p2), .p3(top.p3), .*);

So the hierarchical references for the port binding is fine, but it seems like the hierarchical references for the parameters is not. Is this in line with your intention?

I've attached a test-case that Verilator is happy with, without hierarchical parameter references. To produce the Errors, simply switch in the commented bind statement.

Cheers, Ed

bind_example_2.sv (2 KB) Ed Lander, 02/15/2013 02:41 PM

sc_main.cpp View (373 Bytes) Ed Lander, 02/15/2013 02:41 PM

bind_support_example-verilator-3.845.mk (1.01 KB) Ed Lander, 02/15/2013 02:41 PM

History

#1 Updated by Ed Lander over 6 years ago

P.S. Trial conducted with Verilator 3.845 (first release supporting bind statements)

#2 Updated by Wilson Snyder over 6 years ago

I didn't think it was legal to have dotted parameters. Actually VCS agrees and says "targetmod, "top.param3" The use of a non-constant expression to override a parameter value is illegal."

Am I missing something?

#3 Updated by Ed Lander over 6 years ago

Hi Wilson,

We're using the parameter as an elaboration-time constant, and not sure of how else to express it.

Can we be so bold as to suggest that VCS is wrong?

Cheers, Ed

#4 Updated by Wilson Snyder over 6 years ago

Of course VCS could be wrong. I can't find exact wording either way in IEEE, but no-dots is my understanding and VCS usually has the best SystemVerilog adherence out there. And, it will be a major change to fix this as Verilator resolves all parameters before doing any dotted variables so either way it's not going to happen soon, sorry.

So if you want to be sure, and leave this open, please ask the IEEE committee if this is legal.

To work around perhaps use a $unit parameter than reference that?

parameter param3 = 1;
bind ...
module a;
  ...
endmodule

#5 Updated by Ed Lander over 6 years ago

Ok, thanks Wilson, yes the IEEE SV doc isn't massively explicit on such detail with bind. We're reworking our code to align with your implementation.

Cheers, Ed

#6 Updated by Wilson Snyder over 6 years ago

  • Status changed from New to WillNotFix

Thanks for adapting.

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