module testcase_file ();
integer fd;
initial begin
     fd = $fopen("file.txt");
     $fdisplay(fd, "Hello World\n");
     $fclose(fd);
end
endmodule

$ verilator --cc testcase_fopen.v 
%Error: testcase_fopen.v:4: syntax error, unexpected ')'
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/bin/verilator_bin --cc testcase_fopen.v

diff --git a/src/verilog.y b/src/verilog.y
index fa0a208..a7d084f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2185,6 +2185,7 @@ statementVerilatorPragmas<nodep>:
 foperator_assignment<nodep>:	// IEEE: operator_assignment (for first part of expression)
 		fexprLvalue '=' delayE expr	{ $$ = new AstAssign($2,$1,$4); }
 	|	fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')'	{ $$ = new AstFOpen($3,$1,$5,$7); }
+	|	fexprLvalue '=' yD_FOPEN '(' expr ')'	{ $$ = new AstFOpen($3,$1,$5,  new AstConst($<fl>1,V3Number(V3Number::VerilogString(),$<fl>5,GRAMMARP->deQuote($<fl>5, "w")))); }
 	//
 	//UNSUP	~f~exprLvalue '=' delay_or_event_controlE expr { UNSUP }
 	//UNSUP	~f~exprLvalue yP_PLUS(etc) expr		{ UNSUP }