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problem/question for AUTOLOGIC of array with different elements going to different instances #626

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veripoolbot opened this issue Feb 28, 2013 · 7 comments
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problem/question for AUTOLOGIC of array with different elements going to different instances #626

veripoolbot opened this issue Feb 28, 2013 · 7 comments

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Author Name: David Rogoff
Original Redmine Issue: 626 from https://www.veripool.org
Original Date: 2013-02-28

Hi Wilson,

I've got some more questions for you al I'll start with this one.

I've got code like this:

// header file:
typedef logic [15:0] outbus_t;
parameter outbus_t  zz = 0;
parameter outbus_t  hello = 1;
parameter outbus_t  zorg = 2;
parameter NUM_BUSES = 3



module or_buses
 #(parameter NUM_BUSES = 5)
  (input outbus_t [NUM_BUSES-1:0] buses_from_modules);
endmodule

module mod_a 
  (output  outbus_t output_bus);
endmodule


module top;

`include "header.vh"

or_buses 
  (#AUTOINST_PARAM)
or_buses
  (#AUTOINST);


/* mod_a AUTO_TEMPLATE "__\([a-z]+\)$" (
  .output_bus   (buses_from_modules [ @ ] ),
);  */
mod_a 
  or_buses__zz
     (#AUTOINST);

mod_a 
  or_buses__hello
     (#AUTOINST);

mod_a 
  or_buses__zorg
     (#AUTOINST);

When I expand the AUTOs, AUTOLOGIC is wrong for buses_from_modules since it doesn't know the range.

I tried manually putting in

 outbus_t [NUM_BUSES-1:0]  buses_from_modules;

But I still get a wrong AUTO declaration in addition and then have to remember to delete that line every time I expand the AUTOs.
How do I get the AUTO to work or at least tell it to ignore a signal.

Thanks,

David
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-28T23:47:23Z

I get

mod_a
or_buses__zz
(/AUTOINST/
// Interfaces
.output_bus (buses_from_modules [ zz ] )); // Templated

Which I think is what you asked for. Probably I'm missing something obvious.

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Original Redmine Comment
Author Name: David Rogoff
Original Date: 2013-02-28T23:59:47Z

Sorry- wasn't clear (doing way too many things at once!). The problem is in the /AUTOLOGIC/ declaration. The AUTOINST is fine but AUTOLOGIC doesn't declare the array of buses_from_modules correctly and picks the wrong MSB. I think it said something about a merge issue.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-03-01T00:17:44Z

Your example didn't have a AUTOLOGIC :) But anyhow try the most recent version which includes a recent typedef fix.

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Original Redmine Comment
Author Name: David Rogoff
Original Date: 2013-03-01T17:49:04Z

Thanks Wilson. At least is doesn't add the "merge error" declaration now so I can just manually declare the bus.

OT - I'm also starting to learn more elisp to write my own defuns to get passed the @ and \N limitations. I just take vl-name and vl-cell-name as arguments and do what I need. By the way, can I somehow tell if the "port" I'm working on is a parameter vs a signal port?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-03-03T16:16:14Z

vl-dir will be "parameter" for AUTOINSTPARAM.

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Original Redmine Comment
Author Name: David Rogoff
Original Date: 2013-03-03T20:13:10Z

Thanks Wilson!

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-11-10T15:17:05Z

Manual declaration was proposed earlier which is a workaround for this.

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