Non-vector timing loop warning
Capturing forum discussion thread as formal enhancement request (to be discussed with Jeremy) ... Ref: http://www.veripool.org/boards/3/topics/show/1033
I've attached the example that is upsetting Verilator, which we believe to be an invalid Warning. It's a simplified example of code in our design that Verilator is unhappy with. It's essentially nested conditional statements within a single always block, some assigning values to a variable (sig_c_2) that is called by a function, which changes the value of one of the variables that is tested in the always block (sig_c_1).
Reiterating our theory:
- sig_c_1 is derived from a function calling sig_c_2
- sig_c_2 is being evaluated in the always block where there is a test for sig_c_1
However the result of the test for sig_c_1 isn't resulting in an assignment to itself or sig_c_2.
It's clear that reworking Verilator to break this loop would require some major effort, and we are aware that Jeremy is already working on loop detection and reporting. Please consider this ticket a placeholder for (near) future discussion.
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