Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Non-vector timing loop warning #629

Closed
veripoolbot opened this issue Mar 7, 2013 · 1 comment
Closed

Non-vector timing loop warning #629

veripoolbot opened this issue Mar 7, 2013 · 1 comment
Labels
area: lint Issue involves SystemVerilog lint checking area: scheduling Issue involves scheduling/ordering of events effort: days Expect this issue to require roughly days of invested effort to resolve resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor


Author Name: Ed Lander
Original Redmine Issue: 629 from https://www.veripool.org
Original Date: 2013-03-07


Capturing forum discussion thread as formal enhancement request (to be discussed with Jeremy) ...
Ref: http://www.veripool.org/boards/3/topics/show/1033

I've attached the example that is upsetting Verilator, which we believe to be an invalid Warning. It's a simplified example of code in our design that Verilator is unhappy with. It's essentially nested conditional statements within a single always block, some assigning values to a variable (sig_c_2) that is called by a function, which changes the value of one of the variables that is tested in the always block (sig_c_1).

Reiterating our theory:

 * sig_c_1 is derived from a function calling sig_c_2
 * sig_c_2 is being evaluated in the always block where there is a test for sig_c_1

However the result of the test for sig_c_1 isn't resulting in an assignment to itself or sig_c_2.

It's clear that reworking Verilator to break this loop would require some major effort, and we are aware that Jeremy is already working on loop detection and reporting. Please consider this ticket a placeholder for (near) future discussion.

Cheers,
Ed

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking area: scheduling Issue involves scheduling/ordering of events effort: days Expect this issue to require roughly days of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
@wsnyder wsnyder added the resolution: fixed Closed; fixed label May 15, 2022
@wsnyder
Copy link
Member

wsnyder commented May 15, 2022

Believed fixed in develop-v5 with #3278.

@wsnyder wsnyder closed this as completed May 15, 2022
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
area: lint Issue involves SystemVerilog lint checking area: scheduling Issue involves scheduling/ordering of events effort: days Expect this issue to require roughly days of invested effort to resolve resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Development

No branches or pull requests

2 participants