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Issue #63

False Signal unoptimizable: circular logic warning

Added by Lane Brooks over 10 years ago. Updated about 3 years ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

See attached test case showing the problem. This example shows how bit 0 of a bus is used to generate bit 1 of the same bus. Verilator is falsly detecting this as circular logic. Also shown in this test case is that this example works if the signals are not part of a bus (the `ifdef T_WORKS section).

t_BUG.pl View (432 Bytes) Lane Brooks, 01/30/2009 05:33 PM

t_BUG.v (966 Bytes) Lane Brooks, 01/30/2009 05:33 PM

transmit.v (161 Bytes) Keith Campbell, 05/27/2016 10:05 PM

History

#1 Updated by Wilson Snyder over 8 years ago

  • Category changed from Lint to Unsupported
  • Status changed from New to Feature

Similar UNOPTFLAT woes are also discussed in http://www.veripool.org/boards/2/topics/show/373-UNOPTFLAT-Error

#2 Updated by Keith Campbell about 3 years ago

Also ran into this problem. I can contribute a very simple reproduction case (attached). Any known workarounds for building a regular binary tree network? (e.g. a network that sums an input array with parametrizable size)

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