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Specifically, the signal involved is @conf@ which is an array and it triggers a "UNOPTFLAT" warning by Verilator. However, if we disable the "UNOPTFLAT" warning, Verilator will generate C++ code. But the index of the array is not correct.
In Vsim_top.h, the signal is defined as:
Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 630 from https://www.veripool.org
Original Date: 2013-03-08
Original Assignee: Jie Xu (@jiexu)
For the following code, Verilator generates incorrect code where array index is out of bound.
Specifically, the signal involved is @conf@ which is an array and it triggers a "UNOPTFLAT" warning by Verilator. However, if we disable the "UNOPTFLAT" warning, Verilator will generate C++ code. But the index of the array is not correct.
In Vsim_top.h, the signal is defined as:
But in Vsim_top.cpp::_change_request, these are used as:
The verilog was compiled with
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