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SV Interface indentation issue in module ports #636

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veripoolbot opened this issue Apr 11, 2013 · 3 comments
Closed

SV Interface indentation issue in module ports #636

veripoolbot opened this issue Apr 11, 2013 · 3 comments
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@veripoolbot
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Author Name: Christophe Clienti
Original Redmine Issue: 636 from https://www.veripool.org

SV Interfaces with modports are badly indented. You can reproduce the issue using the folloing code.

//-----------------------------------------------------------
module mymodule (input logic reset_n,
input logic clock,
streambus.sink sink,
streambus.source source,
output logic interrupt_pulse);

logic [31:0]               test;
streambus.source source;

//-----------------------------------------------------------

The same issue is also observed in the signal declaration within the module
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Original Redmine Comment
Author Name: Christophe Clienti
Original Date: 2013-04-11T14:12:22Z

SV Interfaces with modports are badly indented. You can reproduce the issue using the folloing code.

//-----------------------------------------------------------
module mymodule (input logic  reset_n,
                  input logic  clock,
                               streambus.sink sink,
                               streambus.source source,
                  output logic interrupt_pulse);

    logic [31:0]               test;
    streambus.source source;
//-----------------------------------------------------------

The same issue is also observed in the signal declaration within the module

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:16:23Z

Still a problem, maybe someone would like to contribute a patch?

@gmlarumbe gmlarumbe mentioned this issue Jun 8, 2022
Merged
wsnyder pushed a commit that referenced this issue Jun 9, 2022
@gmlarumbe @wsnyder
Fix alignment of declaration of interfaces with modports (#636) (#1770).
4695329 
* verilog-mode.el (verilog-declaration-or-iface-mp-re)
(verilog-declaration-or-iface-mp-re-1-no-macro)
(verilog-declaration-or-iface-mp-re-2-no-macro)
(verilog-get-lineup-indent, verilog-interface-modport-re)
(verilog-pretty-declarations):
Fix alignment of declaration of interfaces with modports (#636) (#1770).
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wsnyder commented Jun 9, 2022

Thanks for another great fix!

@wsnyder wsnyder closed this as completed Jun 9, 2022
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@wsnyder @veripoolbot