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generate problems with non-zero min index array #642

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veripoolbot opened this issue May 10, 2013 · 2 comments
Closed

generate problems with non-zero min index array #642

veripoolbot opened this issue May 10, 2013 · 2 comments
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@wsnyder
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resolution: fixed Closed; fixed

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Author Name: Krzysztof Jankowski
Original Redmine Issue: 642 from https://www.veripool.org
Original Date: 2013-05-10
Original Assignee: Wilson Snyder (@wsnyder)

     parameter SIZE = 4;
     logic[SIZE:1][3:0]  delay;
     genvar              i;
     generate
         for (i = 2; i < (SIZE+1); i++)
         begin
             always_ff @(posedge clock)
             begin
                 delay[i][3:0] <= delay[i-1][3:0];
             end
         end
     endgenerate
     always_comb datao = delay[SIZE][3:0];

Above code snippet doesn't compile, verilator quits with error
??%Error: Internal Error: test2.sv:20: ../V3Ast.cpp:343: Adding already linked node.??
It works fine with delay[SIZE-1:0][3:0]. Full code attached.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-05-10T11:10:16Z

Good example. Simple enough, fixed in git towards 3.847.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-05-11T20:18:10Z

In 3.847.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
tgorochowik pushed a commit to antmicro/verilator that referenced this issue Feb 29, 2024
@RRozak
Merge pull request verilator#642 from antmicro/param_ref
7ade621 
Handle vpiParameter case as reference
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