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Asignments of arithmetic operations embedded in a concatenation cause wrong conditional paths to be taken #646

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veripoolbot opened this issue May 19, 2013 · 2 comments
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resolution: abandoned Closed; not enough information or otherwise never finished

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@veripoolbot
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Author Name: Daniel Bone
Original Redmine Issue: 646 from https://www.veripool.org
Original Date: 2013-05-19


Trying to use a single wire concatenated with a vector to capture an addition overflow was causing a mismatch between the waveform value and the conditional branch taken for the value of that wire.

I suspect the wire is being incremented beyond its range of 0 to 1, causing the if statement to treat it as 2 rather than 0 following 2 assignments via addition overflow.

Solved the issue by using a seperate vector packed with the operands to preform the addition on and then unpack afterwards.

//Code snippet

@reg [5:0] bank_ptr_ff;@

@wire [5:0] bank_ptr_nxt;@

@reg bank_sel_ff;@

@wire bank_sel_nxt;@

@Always (bank_wr or bank_ptr_ff or bank_sel_ff or bank_wr_size)@

@begin@

@if (bank_wr)@

@begin@

@{1'b0, bank_sel_nxt, bank_ptr_nxt} = {bank_sel_ff, bank_ptr_ff} + @
@{1'b0, bank_wr_size};@

@EnD@

@else@

@begin@

@{bank_sel_nxt, bank_ptr_nxt} = {bank_sel_ff, bank_ptr_ff};@

@EnD@

@EnD@

@assign wr_en_nxt = wrap;@

@assign wr_sel_nxt = bank_sel_ff;@

@assign data_o = (wr_sel_ff == 1'b0) ? bank_1_ff : bank_2_ff;@

@assign wr_o = wr_en_ff;@

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-05-19T14:00:12Z


Your example is not valid verilog, you can't have a constant on the left hand side. If you could modify the attached test snippit (see the manual) to pass on another simulator and fail with Verilator I'll fix it.

P.s. wrapping ``` around the code is an easier way to format.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-08-13T10:11:28Z


Closed due to inactivity.

@veripoolbot veripoolbot added the resolution: abandoned Closed; not enough information or otherwise never finished label Dec 22, 2019
tgorochowik pushed a commit to antmicro/verilator that referenced this issue Feb 29, 2024
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Labels
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