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module->net->width incorrect #65
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Original Redmine Comment Devendra Singh wrote:
I have modified files Net.pm and File.pm at my end, also I have provided the modification below contained by "#by devendra" in the line from the files below. I have checked it with an example at my end, but not sure if it will break something else. Let me know if these are appropriate.
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Original Redmine Comment Devendra Singh wrote:
attached the files as text was not very legible. |
Original Redmine Comment Thanks for the patch. I used abs() in the first place you pointed out. This is in git, and will be in the next release. I'm confused about the second part of your patch (lsb=msb=0). I suspect you did that to avoid a undef warning. Undefs are important to disambiguate "wire x" from "wire [0:0] x", so you need to test for undef yourself. P.S. Since you said you grabbed from git: "git diff" will give you a file you can send so you don't need to manually track the changes. |
Original Redmine Comment Devendra Singh wrote:
since width is calculated only if lsb and msb are defined, the width comes as undef for nets with width 1. I am from hardware design background and do not understand correctly...how will it effect if Also I believe parameters are treated as nets in Verilog-Perl and if a parameter is declared as integer then its lsb and msb should be undef, and there should be a difference in treatment for a port/wire and parameter. |
Original Redmine Comment I see your point. I changed ->width to return 1/8/16/32/64 as appropriate for the net type, when it is known and simple, else undef as before. |
Original Redmine Comment In 3.120 |
Author Name: Devendra Singh
Original Redmine Issue: 65 from https://www.veripool.org
Original Date: 2009-02-11
Original Assignee: Wilson Snyder (@wsnyder)
the width provided by the $net->width is incorrect
if the verilog has width declared as bigendian e.g. a verilog declaration [0:2], resultant width returned by $net->width is -1.
Width should be a absolute value and lsb and msb can provide the declaration details (endianess).
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