Author Name: Krzysztof Jankowski
Original Redmine Issue: 652 from https://www.veripool.org
Original Date: 2013-05-24
Original Assignee: Wilson Snyder (@wsnyder)

module width(
     input  logic pick1,
     input  logic [13:0] [1:0]       data1,  //    14 x 2 = 28 bits
     input  logic [ 3:0] [2:0] [1:0] data2,  // 4 x 3 x 2 = 24 bits
     output logic [15:0] [1:0]       datao   //    16 x 2 = 32 bits
);
always_comb datao[13: 0] = (pick1) ? {data1} : {'0, data2};
always_comb datao[15:14] = '0;
endmodule

I'm trying to compile code like above example (original code does build with commercial tools), but I'm getting width mismatch errors:

$ verilator -sc --top-module width ./width.sv

%Warning-WIDTH: width.sv:9: Operator COND expects 28 bits on the Conditional False, but Conditional False's CONCAT generates 25 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: width.sv:9: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's COND generates 28 bits.
%Error: Internal Error: width.sv:9: ../V3Expand.cpp:354: Width mismatch
%Error: Command Failed /usr/local/bin/verilator_bin -sc --top-module width ./width.sv

Does above use some SV construct unsupported by Verilator yet, or is it a known issue?