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Read Parmetarized Verilog File #657

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veripoolbot opened this issue Jun 18, 2013 · 4 comments
Closed

Read Parmetarized Verilog File #657

veripoolbot opened this issue Jun 18, 2013 · 4 comments
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area: parser Issue involves SystemVerilog parsing resolution: abandoned Closed; not enough information or otherwise never finished

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Author Name: Amir Yazdanbakhsh
Original Redmine Issue: 657 from https://www.veripool.org
Original Date: 2013-06-18

Hi,

I was trying to read a parameterized Verilog file with Verilator. But it seems it generates and error.
Attached you can see my Verilog file.

Thanks
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-06-18T16:36:02Z

This is an incomplete example - please provide a complete example that has been checked on another simulator, see the docs for how to do this, thanks.

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Original Redmine Comment
Author Name: Amir Yazdanbakhsh
Original Date: 2013-06-18T16:36:52Z

Would you please tell me where in the Document? I can not find it!

Thanks

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Original Redmine Comment
Author Name: Joe Eiler
Original Date: 2013-06-18T19:01:10Z

See the BUGS section in the end of the manual for how to create a test.

[http://www.veripool.org/projects/verilator/wiki/Manual-verilator]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-08-13T10:10:08Z

Closing due to inactivity.

@veripoolbot veripoolbot added area: parser Issue involves SystemVerilog parsing resolution: abandoned Closed; not enough information or otherwise never finished labels Dec 22, 2019
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