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SystemVerilog interfaces: Internal error when connecting interfaces #658

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veripoolbot opened this issue Jun 18, 2013 · 9 comments
Closed

SystemVerilog interfaces: Internal error when connecting interfaces #658

veripoolbot opened this issue Jun 18, 2013 · 9 comments
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resolution: abandoned Closed; not enough information or otherwise never finished

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Author Name: Ed Lander
Original Redmine Issue: 658 from https://www.veripool.org
Original Date: 2013-06-18

Hi,

We are seeing an internal error when connecting SystemVerilog interfaces. Verilator happily compiles the interface file, but then falls over on elaboration:

%Error: Internal Error: <file_path>:<linenum>: ../V3Scope.cpp:234: Can't locate varref scope

The interface file itself contains two interface definitions (a channel interface and a multi-channel interface, made up of two channel interfaces). I've attached a stripped down file that is safe for the public domain, alas Verilator is not entirely happy with it; I need to comment out lines 65 - 67 before I get the same Error message as with the full file:

%Error: Internal Error: ../V3LinkLevel.cpp:89: No module found to process

Note: once the (super) interface is instantiated in our design that Internal Error message goes away.

With regards to how we wire the interface into our design, we use the following syntax in our module declaration:

  block_channel_ifce.master <channel_name>,

And we're assigning values / signals to the interface using the following syntax:

       assign <signal_assigned>	= <interface>.<interface_wire>;

At the next level up, we do:

  block_channel_ifce.master <channel1_name>,
  block_channel_ifce.master <channel2_name>,

And:

<module> <instance1> (
  .block_channel_ifce	(<interface1_name>),

...

<module> <instance2> (
  .block_channel_ifce	(<interface2_name>),

Cheers,
Ed
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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-18T16:37:58Z

Important clarification: whilst we define multiple / nested interfaces, our design isn't actually using the nested style (other EDA tools are unhappy with it). I'll enhance the example file to align with our integration and see if I can throw up the internal Error.

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-19T11:17:01Z

Revised example attached. Internal error not repeated; i'll try recoding our complex example ...

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-19T11:45:23Z

Typo in example corrected.

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-19T13:13:17Z

Clean example attached (to be made more complex).

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-19T13:58:35Z

Example updated (now with two instances of an interface propagating down through two levels of hierarchy). Clean output from Verilator.

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-19T14:34:54Z

I've replicated our example almost exactly now (file attached), but Verilator is happy with it (cannot recreate internal error).

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-06-21T00:28:38Z

Ok, so the last example you gave already passes on git head, right? So I'm not sure if there's something for me to look at here or not....

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-06-21T09:11:49Z

Hi Wilson, yes indeed sadly I cannot recreate the internal error with our simplified example, so there is nothing for you to look at. I'll try and debug the internal error at our side further ...
Cheers, Ed

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-01-18T18:32:04Z

Closing - recent versions work.

@veripoolbot veripoolbot added the resolution: abandoned Closed; not enough information or otherwise never finished label Dec 22, 2019
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