Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #662

Clock gated signals not synchronised if used as a logical input

Added by Charlie Brej almost 6 years ago. Updated almost 6 years ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

When a clock gated signal is used as a logical input it loses it's synchronization with the input clock. This is rarely a problem as the clock is only sensed with edge sensitive always statements, but if it is ever an input to logic it becomes unsynchronized again.

Test case attached. Removing the "$display("Clock is %d", clk2);" line makes the test pass again.

t_000_clkgate.v (1.05 KB) Charlie Brej, 06/28/2013 12:33 PM

t_000_clkgate.pl View (463 Bytes) Charlie Brej, 06/28/2013 12:33 PM

History

#1 Updated by Wilson Snyder almost 6 years ago

  • Status changed from New to Confirmed

Haven't had a chance to look at this yet, sorry.

Also available in: Atom