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Clock gated signals not synchronised if used as a logical input #662

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veripoolbot opened this issue Jun 28, 2013 · 2 comments
Closed

Clock gated signals not synchronised if used as a logical input #662

veripoolbot opened this issue Jun 28, 2013 · 2 comments
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area: scheduling Issue involves scheduling/ordering of events area: wrong runtime result Issue involves an incorrect runtine result from Verilated model effort: weeks Expect this issue to require weeks or more of invested effort to resolve resolution: fixed Closed; fixed

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Author Name: Charlie Brej
Original Redmine Issue: 662 from https://www.veripool.org
Original Date: 2013-06-28

When a clock gated signal is used as a logical input it loses it's synchronization with the input clock. This is rarely a problem as the clock is only sensed with edge sensitive always statements, but if it is ever an input to logic it becomes unsynchronized again.

Test case attached. Removing the "$display("Clock is %d", clk2);" line makes the test pass again.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-07-03T00:39:26Z

Haven't had a chance to look at this yet, sorry.

@veripoolbot veripoolbot added area: scheduling Issue involves scheduling/ordering of events area: wrong runtime result Issue involves an incorrect runtine result from Verilated model effort: weeks Expect this issue to require weeks or more of invested effort to resolve status: blocked Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned' labels Dec 22, 2019
@wsnyder wsnyder added resolution: fixed Closed; fixed and removed status: blocked Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned' labels May 15, 2022
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wsnyder commented May 15, 2022

Believed fixed in develop-v5 with #3278.

@wsnyder wsnyder closed this as completed May 15, 2022
tgorochowik pushed a commit to antmicro/verilator that referenced this issue Feb 29, 2024
@RRozak
Merge pull request verilator#662 from antmicro/clean_typedefs
477df84 
Don't return AstRefDType in process_typedef
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area: scheduling Issue involves scheduling/ordering of events area: wrong runtime result Issue involves an incorrect runtine result from Verilated model effort: weeks Expect this issue to require weeks or more of invested effort to resolve resolution: fixed Closed; fixed
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