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Author Name: Wkong Zhu Original Redmine Message: 1199 from https://www.veripool.org
I use verilog-mode the most updated version. 05-26. When use \Ctl-c \Ctl t D,it really works, but the code generated is not as pretty as it should be.
module tst (/*AUTOARG*/ // Outputs c, // Inputs a, b ) ; input [1:0] a, b; output [1:0] c; /*AUTOREG*/ /*AUTOWIRE*/ assign d = ~a; assign c = a & d; endmodule // tst
when I put cursor at d, and type \ctl-c \ctl-t D, it looks like below:
module tst (/*AUTOARG*/ // Outputs c, // Inputs a, b ) ; reg [1:0 ] d; input [1:0] a, b; output [1:0] c; /*AUTOREG*/ /*AUTOWIRE*/ assign d = ~a; assign c = a & d; endmodule // tst
The text was updated successfully, but these errors were encountered:
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Author Name: Wkong Zhu
Original Redmine Message: 1199 from https://www.veripool.org
I use verilog-mode the most updated version. 05-26.
When use \Ctl-c \Ctl t D,it really works, but the code generated is not as pretty as it should be.
when I put cursor at d, and type \ctl-c \ctl-t D, it looks like below:
The text was updated successfully, but these errors were encountered: