Author Name: Arnaud Turier
Original Redmine Issue: 671 from https://www.veripool.org
Original Date: 2013-08-28
Original Assignee: Wilson Snyder (@wsnyder)

Hi,

I got an issue when the parser reads a mintypmax expression.

Such a parameter definition makes the parser to report a syntax error:
parameter tcyc = 5 : 10 : 20 ;

$ vhier mytest.v
%Error: mytest.v:5: syntax error, unexpected ':', expecting ';'

However, if the mintypmax expression is surround by brackets, it is OK:
parameter tacc = (2 : 4 : 8) ;

I checked in the documentation regarding Verilog syntax and it is seems it is not mandatory to surround by brackets the mintypmax expressions in parameter definitions. I tried to invoke vhier with --language option set to '1800-2012' and I got the same error.

I am working on Verilog models from third parties I can not modify.

Thank you