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Problem with bit selection from const variable #693

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veripoolbot opened this issue Oct 31, 2013 · 2 comments
Closed

Problem with bit selection from const variable #693

veripoolbot opened this issue Oct 31, 2013 · 2 comments
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resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 693 from https://www.veripool.org
Original Date: 2013-10-31
Original Assignee: Wilson Snyder (@wsnyder)


Compiling the following code will fail

const logic unsigned [31:0] var_const;
logic [7:0] res_const;
assign res_const = var_const[7:0];  // Error line, not able to select part of const

with error:

Illegal bit or array select; type already selected, or bad dimension: type is 
Illegal range select; type already selected, or bad dimension: type is

Remove the @const@ will fix the problem of course. Not sure if the use here is compliant with standard or not. An attempt to fix this together with test case can be pulled here: https://github.com/jiexu/verilator/ constSel.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-11-01T02:39:30Z


Fixed in git towards 3.854.

"const" to my knowledge hasn't been tested very well, so I wouldn't be surprised if there are additional issues. Note also const isn't strongly enforced.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-11-27T01:15:40Z


In 3.854.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
tgorochowik pushed a commit to antmicro/verilator that referenced this issue Feb 29, 2024
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Labels
resolution: fixed Closed; fixed
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