Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-11-15T12:06:12Z

The state remains as said in #�, they are unsupported with a patch if someone wants to put in the effort to improve them.

Meanwhile the standard practice is to make standard modules with the same functions as the primitives.

Original Redmine Comment
Author Name: Kaalia Kahn
Original Date: 2013-11-15T15:24:55Z

Hi Wilson,

I hope you are well. I have done as you said i.e, replacing primitives with equivalent RTL code. The simulation works but the answer is not correct. This is for gate-level simulation of opencores AES-128 design. I have done the RTL simulation of AES-128 as well with Verilator. RTL simulation is giving the expected output but Gate-level is not. How to resolve this mismatch easily?

I am attaching the tar file. Please take a look.

I want to make this available as opensource design to your website once it is done.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-11-15T15:53:28Z

Sorry, I am a little too overwhelmed to debug individual issues. I would suggest you run it under a different simulator and compare waveforms to find where it differs. A typical problem spot is generated clocks.

If you find a issue not described in the manual please make a test case in the format described in the manual. If your issue is urgent chances are you will need to provide a patch yourself; unfortunately this is the nature of open source, you are not paying for support.