VCD trace support for structure and interface #705
Labels
resolution: fixed
Closed; fixed
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 705 from https://www.veripool.org
Original Date: 2013-12-06
Original Assignee: Wilson Snyder (@wsnyder)
It is great that now verilator supports a lot of system-verilog features. But it seems the vcd tracing of structure and interface are not supported? This makes our debugging very difficult as we can't compare the waveform with the one generated by VCS.
The text was updated successfully, but these errors were encountered: