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VCD trace support for structure and interface #705

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veripoolbot opened this issue Dec 6, 2013 · 4 comments
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VCD trace support for structure and interface #705

veripoolbot opened this issue Dec 6, 2013 · 4 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 705 from https://www.veripool.org
Original Date: 2013-12-06
Original Assignee: Wilson Snyder (@wsnyder)


It is great that now verilator supports a lot of system-verilog features. But it seems the vcd tracing of structure and interface are not supported? This makes our debugging very difficult as we can't compare the waveform with the one generated by VCS.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-12-07T13:36:25Z


It does trace structures, the 'names' of the structure members however may differ from what you expect. For example in unions I think it uses only the first union name, due to limitations in the VCD format.

In some cases it will not trace very large structures - see the generated Trace.cpp file for comments on what signals it considers too large. --trace-max-array and --trace-max-width can override these.

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Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2013-12-09T07:06:02Z


I am aware of the max-array and max-width configuration. I think it is not the problem here.

For example, for the following structure:

  typedef struct packed {
     logic               [15:0] data;
  } data_t;

  data_t data_r;

@data_r@ is not traced, and in @trace__slow.cpp@ there is a comment "data_r // Ignored: Unsupported: Multi-dimensional array".

So the real problem maybe is the multi-dimensional array?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-12-14T21:53:24Z


Fixed in git towards 3.855. Please check it works with your larger test.

I didn't see anything specially broken with interfaces, I presume it was the same issue as with modules.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-01-18T18:30:17Z


In 3.855.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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