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verilator fails to regenerate cpp code when verilog source is updated #707

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veripoolbot opened this issue Jan 17, 2014 · 3 comments
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Derek Lockhart
Original Redmine Issue: 707 from https://www.veripool.org
Original Date: 2014-01-17


Running Verilator 3.855 devel rev verilator_3_854-8-gb5f5b1f on OSX Mavericks, verilator fails to regenerate cpp code when verilog source is updated. This problem is intermittent, but reproducible.

Given some simple verilog source:

module Test
(
  input  [  15:0] in0,
  input  [  15:0] in1,
  output [  15:0] yyy 
);
  reg    [  15:0] yyy;
  always @ (*) begin
     yyy = in0 & in1;
  end 
endmodule

Changing the name of the output signal and running verilator does not consistently regenerate cpp source.

Below shows a bash session in which I perform the following steps:

  1. generate cpp source for Test.v (code cited above) using verilator
  2. use grep to search for the strings xxx and yyy in the verilog source and generated cpp
  3. use the sed command to change all references of xxx to yyy
  4. run verilator yet again
  5. use grep to search for the strings xxx and yyy in the verilog source and generated cpp
$ verilator -cc Test.v -top-module Test -trace -Wno-lint -Wno-UNOPTFLAT
$ grep -E "xxx|yyy" Test.v obj_dir/VTest.cpp 
Test.v:  output [  15:0] xxx
Test.v:  reg    [  15:0] xxx;
Test.v:    xxx = in0 & in1;
obj_dir/VTest.cpp:    xxx = VL_RAND_RESET_I(16);
obj_dir/VTest.cpp:    vlTOPp->xxx = ((IData)(vlTOPp->in0) & (IData)(vlTOPp->in1));

$ sed -i '' 's/xxx/yyy/g' Test.v 
$ verilator -cc Test.v -top-module Test -trace -Wno-lint -Wno-UNOPTFLAT
$ grep -E "xxx|yyy" Test.v obj_dir/VTest.cpp 
Test.v:  output [  15:0] yyy
Test.v:  reg    [  15:0] yyy;
Test.v:    yyy = in0 & in1;
obj_dir/VTest.cpp:    xxx = VL_RAND_RESET_I(16);
obj_dir/VTest.cpp:    vlTOPp->xxx = ((IData)(vlTOPp->in0) & (IData)(vlTOPp->in1));

$ verilator -cc Test.v -top-module Test -trace -Wno-lint -Wno-UNOPTFLAT
$ grep -E "xxx|yyy" Test.v obj_dir/VTest.cpp 
Test.v:  output [  15:0] yyy
Test.v:  reg    [  15:0] yyy;
Test.v:    yyy = in0 & in1;
obj_dir/VTest.cpp:    xxx = VL_RAND_RESET_I(16);
obj_dir/VTest.cpp:    vlTOPp->xxx = ((IData)(vlTOPp->in0) & (IData)(vlTOPp->in1))

I've tried many variations in an attempt to find a pattern. Sometimes code generation works just fine, and each time the source is change cpp code is regenerated. Other times I can change the source, and run verilator many times without success.

I could not find any flags that enable a 'force recompile' option with the verilator docs, so I'm not sure if this is due to a timestamp/caching issue within verilator. Running with --debug did seem to fix the issue, but I would prefer not to have the extra output generated by the debug build.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-01-18T02:07:58Z


Unless the file has the same size and modification time (to the second) it should work. Might you be changing within one second? Anyhow try --no-skip-identical.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-02-10T01:39:39Z


Fixed in git towards 3.856.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-12T00:05:34Z


In 3.856.

@veripoolbot veripoolbot added area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed labels Dec 22, 2019
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Labels
area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed
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