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"q <= #1 'hx;" compile fail #712
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Original Redmine Comment See #�. It is not related to spaces, as "q <= 1 'hx" is a number. |
Original Redmine Comment Hi redmine, |
Original Redmine Comment I checked in page 20 of "IEEE Std 1364-2001.pdf", it is illegal to have a space between "1" and "'hx" to express a hex number "1'hx". Am I right? |
Original Redmine Comment Spaces are definitely legal. Page 20 of my 2001 spec isn't even about this topic, so I'm not sure which version you are referring to. Anyhow they are separate tokens per Appendix A: hex_number ::= [ size ] hex_base hex_value The problem is as Verilog-Perl was originally written the number parsing is done at lex stage, and fixing that is a big change that will break other's parsers vs. this one bug. |
Original Redmine Comment BTW if you would like to attack fixing it, I can provide pointers of how to start. Alternatively you could write a custom Verilog::Preproc that searches-and-replaces as the code is read in. |
Original Redmine Comment Please post followups to #�. |
Original Redmine Comment Sorry, you are right, it is in page 7(I used the page number showed by pdf reader). Maybe I made some misunderstandings of the description. size ::= non_zero_unsigned_number (* means Embedded spaces are illegal) No space is allowed in "size" or between "[size]" and "hex_base" Thank you for your reminding of the perl script change. |
Author Name: Aaron Zheng
Original Redmine Issue: 712 from https://www.veripool.org
Original Date: 2014-02-09
In version 3.402, "q <= #1 'hx;" compiles as:
q
<=
1 'hx
;
"1 'hx" should be two numbers as a space seperate them.
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