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Author Name: Lane Brooks
Original Redmine Issue: 716 from https://www.veripool.org
Original Date: 2014-02-14
Original Assignee: Wilson Snyder (@wsnyder)
I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Following is an example. I am not using the latest version of verilator, so I am not sure if it is has already been fixed.
module port_test
(
input A=asdf,
input B
);
endmodule
Sorry for not creating a test and submitting it that way.
The text was updated successfully, but these errors were encountered:
Author Name: Lane Brooks
Original Redmine Issue: 716 from https://www.veripool.org
Original Date: 2014-02-14
Original Assignee: Wilson Snyder (@wsnyder)
I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Following is an example. I am not using the latest version of verilator, so I am not sure if it is has already been fixed.
Sorry for not creating a test and submitting it that way.
The text was updated successfully, but these errors were encountered: