Crash with port = syntax error
I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Following is an example. I am not using the latest version of verilator, so I am not sure if it is has already been fixed.
module port_test ( input A=asdf, input B ); endmodule
Sorry for not creating a test and submitting it that way.
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