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Issue #716

Crash with port = syntax error

Added by Lane Brooks over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Low
Assignee:
Category:
Lint
% Done:

0%


Description

I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Following is an example. I am not using the latest version of verilator, so I am not sure if it is has already been fixed.

module port_test
  (
   input A=asdf,
   input B
   );
endmodule

Sorry for not creating a test and submitting it that way.

History

#1 Updated by Wilson Snyder over 5 years ago

  • Subject changed from Port lexing error to Crash with port = syntax error
  • Category set to Lint
  • Status changed from New to Assigned
  • Assignee set to Wilson Snyder
  • Priority changed from Normal to Low

Thanks, I'll see what's up.

#2 Updated by Wilson Snyder over 5 years ago

  • Status changed from Assigned to Resolved

Fixed in git towards 3.856.

#3 Updated by Wilson Snyder over 5 years ago

  • Status changed from Resolved to Closed

In 3.856.

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