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Question: Removing comments after AUTO ports or wires #725

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veripoolbot opened this issue Mar 24, 2014 · 3 comments
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Question: Removing comments after AUTO ports or wires #725

veripoolbot opened this issue Mar 24, 2014 · 3 comments
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@veripoolbot
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Author Name: Eric Jackowski
Original Redmine Message: 1329 from https://www.veripool.org


Is there a way to remove the comments after the signal declaration in the AUTOs?

For example, using autowire generates the below code:

/AUTOWIRE/

wire my_signal; // From u_my_module of my_module.v

So how can I remove "// From u_my_module of my_module.v" from the code?

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-24T21:17:08Z


There isn't at present a way to do this. There are a lot of
different opinions on what these comments should show - more
than one per company style. Assuming it's your company
style that prompts this I've found usually they get won
over.

But to do this, you could write a verilog-auto-hook
which deletes them after-the-fact.

Or, you could edit where verilog-sig-comment is called to
not print when a new variable is set, e.g.

+(defvar verilog-auto-comments t "...")
....

  • (if (or (not (verilog-sig-comment sig))
    
  • (if (and (or (not (verilog-sig-comment sig))
    
  •          verilog-auto-comments)
                  (equal "" (verilog-sig-comment sig)))
         (insert "\n")
    

Roughly.... as I sent this to someone and they said it wasn't enough - didn't get more details.

I might get convinced to some code that makes this optional after you've used and debugged it for a few months.

@veripoolbot
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Original Redmine Comment
Author Name: Mobile Man
Original Date: 2016-04-21T19:25:01Z


There are many users in my company who would like to have the comments removed as well.

What is the logic behind adding the comments? Do people rely on the comments to see where a signal goes?
I personally don't neither do those who I have talked to.

In any case, it would be nice to have this as an option.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-04-25T10:15:57Z


Added "verilog-auto-wire-comment: nil" in verilog-mode-2016-04-23-5f6855e-vpo.

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