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Support enum type checking lint checks #726

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veripoolbot opened this issue Mar 22, 2014 · 1 comment
Closed

Support enum type checking lint checks #726

veripoolbot opened this issue Mar 22, 2014 · 1 comment
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area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Jeff Bush (@jbush001)
Original Redmine Issue: 726 from https://www.veripool.org
Original Date: 2014-03-22

Pretty much any signal with the proper width can be assigned to an enum.

	typedef enum logic[1:0] {
		FOO_A,
		FOO_B,
		FOO_C,
		FOO_D
	} foo_t;
	
	foo_t foo;
	
	always_comb
	begin
		foo = 2'd2;
	end

There should be an error if it is assigned without an explicit cast.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-25T00:27:28Z

Yes, Verilator is weak to almost non-existent in type checks. Needs work.

@veripoolbot veripoolbot added area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
wsnyder added a commit that referenced this issue Jan 2, 2022
@wsnyder
Misc internal and test work towards enum type checks (#726).
bf97296
wsnyder added a commit that referenced this issue Nov 13, 2022
@wsnyder
Add ENUMVALUE warning when value misused for enum (#726).
d25834e
@wsnyder wsnyder added the resolution: fixed Closed; fixed label Nov 13, 2022
@wsnyder wsnyder closed this as completed Nov 13, 2022
mglb pushed a commit to antmicro/verilator that referenced this issue Dec 7, 2022
@wsnyder @mglb
Add ENUMVALUE warning when value misused for enum (verilator#726).
58b50e5
@wsnyder wsnyder mentioned this issue Dec 15, 2022
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area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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