Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Logical Or is outputted as bitwise Or in C++ code generated by verilator #734

Closed
veripoolbot opened this issue Apr 7, 2014 · 1 comment
Closed

Logical Or is outputted as bitwise Or in C++ code generated by verilator #734

veripoolbot opened this issue Apr 7, 2014 · 1 comment
Labels
resolution: wontfix Closed; work won't continue on an issue or pull request

Comments

@veripoolbot
Copy link
Contributor

Author Name: Sharad Bagri
Original Redmine Issue: 734 from https://www.veripool.org
Original Date: 2014-04-07

Verilator is used to convert b12.v to Vb12.cpp (both attached). In line 412 of Vb12.cpp the if condition is "if (((((((((0 == (IData)(vlTOPp->v__DOT__gamma)) | (1 == (IData)(vlTOPp->v__DOT__gamma))) | (2 == (IData)(vlTOPp->v__DOT__gamma))) | (3 == (IData)(vlTOPp->v__DOT__gamma))) | (4 == (IData)(vlTOPp->v__DOT__gamma))) | (5 == (IData)(vlTOPp->v__DOT__gamma))) | (6 == (IData)(vlTOPp->v__DOT__gamma))) | (7 == (IData)(vlTOPp->v__DOT__gamma)))) {"

Ideally it is logical or, so it should be like
"if (((((((((0 == (IData)(vlTOPp->v__DOT__gamma)) || (1 == (IData)(vlTOPp->v__DOT__gamma))) || (2 == (IData)(vlTOPp->v__DOT__gamma))) || (3 == (IData)(vlTOPp->v__DOT__gamma))) || (4 == (IData)(vlTOPp->v__DOT__gamma))) || (5 == (IData)(vlTOPp->v__DOT__gamma))) || (6 == (IData)(vlTOPp->v__DOT__gamma))) || (7 == (IData)(vlTOPp->v__DOT__gamma)))) {"

Can this issue be fixed? I need it because I am using the if clause to put it as a constraint in SMT solver which works differently for logical and bitwise or
@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-07T20:18:07Z

There are a hundreds of optimizations that Verilator does, and this is only the tip of a huge iceberg. If you run more complicated designs you'll find lots of other things are going to be broken. Sorry, but I really don't have time to make the code in a form that you need, but if you want to track that one down yourself that specific optimization is in V3Const.cpp.

@veripoolbot veripoolbot added the resolution: wontfix Closed; work won't continue on an issue or pull request label Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
resolution: wontfix Closed; work won't continue on an issue or pull request
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@veripoolbot