Verilator bug in signed/unsigned expression eval #737
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: fixed
Closed; fixed
Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 737 from https://www.veripool.org
Original Date: 2014-04-09
Original Assignee: Wilson Snyder (@wsnyder)
The term "(p1 + p2)" below is part of an unsigned expression and thus should
be zero-extended. Verilator fb4928b however performs signed bit extension
and thus returns an incorrect result.
Crosscheck: Vivado 2013.4, XST 14.7, Quartus 13.1, Xsim 2013.4 and Modelsim
10.1d implement this correctly.
Self-contained test case:
http://svn.clifford.at/handicraft/2014/verilatortest/test006.v
http://svn.clifford.at/handicraft/2014/verilatortest/test006.cc
http://svn.clifford.at/handicraft/2014/verilatortest/test006.sh
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