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"assert" under "if" with no begin/end causes internal error #743

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veripoolbot opened this issue Apr 17, 2014 · 1 comment
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"assert" under "if" with no begin/end causes internal error #743

veripoolbot opened this issue Apr 17, 2014 · 1 comment
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resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Chandan Egbert
Original Redmine Issue: 743 from https://www.veripool.org
Original Date: 2014-04-17


The code below causes Verilator to fail with the error message

%Error: Internal Error: t/t_assert_if.v:17: ../V3EmitC.cpp:665: Unknown node type reached emitter: VASSERT

Uncommenting the "begin" and "end" around the assertion makes the problem go away. This used to work fine at least till version 3.852

This is the failing code:

module t (/*AUTOARG*/
           // Inputs
           clk
           );

     input clk;

     integer cyc;
     initial
         cyc=1;

     always @ (posedge clk) begin
         if (cyc!=0) begin
	        cyc <= cyc + 1;

             if (cyc==7) // begin
                 assert (cyc[0] == cyc[1]);
             // end

	        if (cyc==10) begin
	            $write("*-* All Finished *-*\n");
	            $finish;
	        end
         end
     end

endmodule


@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-17T02:34:13Z


This was only in the development version, not the release, and was a result of fixing #�.

Fixed in git. Also did quick audit and found another few cases, but unlikely to get hit.

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
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Labels
resolution: fixed Closed; fixed
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