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Uncommenting the "begin" and "end" around the assertion makes the problem go away. This used to work fine at least till version 3.852
This is the failing code:
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc;
initial
cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==7) // begin
assert (cyc[0] == cyc[1]);
// end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
The text was updated successfully, but these errors were encountered:
Author Name: Chandan Egbert
Original Redmine Issue: 743 from https://www.veripool.org
Original Date: 2014-04-17
The code below causes Verilator to fail with the error message
Uncommenting the "begin" and "end" around the assertion makes the problem go away. This used to work fine at least till version 3.852
This is the failing code:
The text was updated successfully, but these errors were encountered: